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Memory Maps
The left-most map in Table 5-1 is the generic, high-level, memory map applicable to the V1 ColdFire
family. Memory map areas shown for RAM, ROM and flash are a superset for the family. Lesser amounts
of all three will usually be included on specific devices. The memory map for the MMA955xL platform
is shown on the right.
The slave peripherals section of the memory map is further broken down as shown in Table 5-2 .
MMA955xL microcontrollers include off-platform, 8-bit and 16-bit peripheral buses. The bus bridges
from the ColdFire system bus to off-platform buses are capable of serializing 32-bit accesses into two
16-bit accesses or four 8-bit accesses. This can be used to speed access to properly aligned peripheral
registers. Not all peripheral registers are aligned to take advantage of this feature.
The off-platform 8- and 16-bit interfaces operate at the same speed as the CPU.
CPU accesses to those parts of the memory map marked as “Unimplemented” in Table 5-1 result in an
illegal address reset if CPUCR[ARD] = 0 or an address error exception if CPUCR[ARD] = 1.
Table 5-2. High-level peripheral memory map
Peripheral
RGPIO
Slave I 2 C
I 2 C
SIM
CLKGEN
MTIM16
IRQ
Port Control module
Port Control module
TPM
PDB
Flash Controller
AFE
INTC
Description
Rapid General-Purpose I/O
Slave I 2 C
Inter-Integrated IC
System Integration Module
CLKGEN
16-Bit Modulo Timer
External Interrupt Module
Port I/O Control Module 0
Port I/O Control Module 1
Two-Channel, Timer/Pulse-Width
Modulator
Programmable Delay Block
Flash Controller
Analog Front End
V1 ColdFire Interrupt Controller
Instance name
RGPIO
SI 2 C
MI 2 C
SIM
CK
MTIM
IRQ
PT0
PT1
TPM
PDB
FC
AFE
INTC
Native bus
width
16
8
8
8
8
8
8
8
8
8
16
16
16
8
Base address
0x(00)C0_0000
0x(FF)FF_8000
0x(FF)FF_8040
0x(FF)FF_8060
0x(FF)FF_8080
0x(FF)FF_80A0
0x(FF)FF_80C0
0x(FF)FF_80E0
0x(FF)FF_8100
0x(FF)FF_8120
0x(FF)FF_EC00
N/A 1
N/A 2
0x(FF)FF_FFC0 3
1
2
The FC registers are only available under Superviser mode.
The AFE registers are only available under Superviser mode.
3 The INTC_FRC register is the first in the INC memory map, and is located at the base address + $10, or (FF)FF_FFD0.
The lower 32 KB of flash memory (16 KB in the MMA955xL platform) and slave peripherals section of
the memory map are most efficiently accessed using the ColdFire absolute, short-addressing mode. RAM
MMA955xL Intelligent, Motion-Sensing Platform Hardware Reference Manual, Rev. 1.0
46
Freescale Semiconductor, Inc.
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